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These results will be presented on June 20 at the VLSI Technology Symposium, in session T8: Advanced FinFET and GAA.
June 19, 2018
By: Anthony Locicero
Copy editor, New York Post
At this week’s 2018 Symposia on VLSI Technology and Circuits, imec presented considerable progress in enabling germanium nanowire pFET devices as a practical solution to extend scaling beyond the 5nm node. In a first paper, the research center unveiled an in-depth study of the electrical properties of strained germanium nanowire pFETs. A second paper presents the first demonstration of vertically-stacked gate-all-around highly-strained germanium nanowire pFETs. “With a number of scaling boos...
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